1. Technical Field of the Invention
The present invention relates to memory circuits such as static random access memories and related methods.
2. Description of Related Art
As is known, integrated circuits are used in a wide variety of electronic equipment, including portable, or handheld, devices. Such handheld devices include personal digital assistants (PDA), CD players, MP3 players, DVD players, AM/FM radio, pagers, cellular telephones, computer memory extension (commonly referred to as a thumb drive), etc. Each of these handheld devices includes one or more integrated circuits to provide the functionality of the device. As an example, a handheld FM radio receiver may include multiple integrated circuits to support the reception and processing of broadcast radio signals in order to produce an audio output that is delivered to the user through speakers, headphones or the like. Many such integrated circuits include a processing device that executes a program that includes a sequence of instructions that are stored in a memory device such as a random access memory (RAM). These devices are typically powered from a small battery that has a limited capacity. Reduced power consumption is an important consideration for these devices in order to increase the amount of time the device can operate before the battery needs to be recharged or replaced.
FIG. 1 presents a schematic block diagram representation of a prior art RAM 240. In particular, a static RAM (SRAM) configuration is disclosed that includes an array of individual memory cells such as memory cell 206, that store binary values and that are arranged in a row and column format for ease in binary addressing. A particular memory cell, such as memory cell 206, is accessed by decoding the address 210 with row decoder 200 and column decoder 202. Row decoder 200 selects the particular wordline 212 that corresponds to the row of memory cells that contains memory cell 206. Column decoder 202 selects the particular complementary bitlines 214 and 216, driven by bitline conditioner 204, that correspond to the column of memory cells that contains memory cell 206. Column multiplexer (MUX) 208 couples the selected bitlines 214 and 216 to sense amplifier 224 and data buffer 226. Data are written to individual memory cells from data in line 222 and data buffer 226. Data are read from individual memory cells by sense amplifier 224 and are output on data out line 220.
FIG. 2 presents a block/schematic diagram representation of a prior art bitline conditioner 204 and column multiplexer 208. P-channel metal oxide semiconductor (PMOS) transistors 232 precharge bitlines 214 and 216 in response to a bitline (BL) precharge signal 230. Column MUX 208 includes PMOS transistors 234 that, when turned on by column enable signal 218 during a read operation, pass the signals on the bitline 214 and 216 to sense amplifier inputs 236 and 238. When wordline 212 is activated, the voltage difference between bitlines 214 and 216 is passed to sense amplifier inputs 236 and 238 for conversion to data out 220 by sense amplifier 224. N-channel metal oxide semiconductor (NMOS) transistors 235, during a write operation, passes Vss (or a logic low level) to one of the bitlines 214 and 216 in response to data from data buffer 226.
The use of PMOS transistors 232 and 234 in bitline conditioner 204 and both PMOS transistors 234 and NMOS transistors 235 in column MUX 208 provides for a relatively reliable design, however, this configuration requires greater memory bit cell array peripheral area and consumes more power when compared with the alternative prior art design shown in FIG. 3 that follows.
FIG. 3 presents a block/schematic diagram representation of an alternative prior art bitline conditioner 205 and column multiplexer 209. In particular, NMOS transistors 233 are used to implement bitline conditioner 205 and an NMOS only column MUX 209 is implemented with transistors 235.
One of the common ways to save power of a memory is a block activation or segmented array architecture. This segmented configuration decreases the length of the bitlines and lowers the bitline capacitance, allowing for faster bitline discharge and consequently faster read operations or conversely, lower power consumption. However, the silicon area overhead created by the greater memory peripheral area makes these segmented configurations costly to implement because each memory segment requires it own bitline conditioner and column multiplexer. Because this design uses less peripheral overhead than the prior art circuit described in FIG. 2, the alternative prior art design of FIG. 3 is more suitable for a segmented array memory architecture. In particular, NMOS transistors 233 occupy less area than PMOS transistors 232 and the elimination of inverter 217 and PMOS transistor 234 also saves space in the design that is replicated for each bitline pair.
However, NMOS transistors 233 can generate an unpredictable precharge level due to NMOS transistor leakage, variations in drain voltage, etc. In particular, if the precharge level increases to a voltage level greater than the drain voltage VDD, minus the NMOS threshold voltage VT, the time until the bitline voltages 214 and 216 are transferred to the sense amplifier side of column MUX transistors 235 becomes unpredictable.
In any of these prior art memories, when the bitline differential is not large enough to overcome mismatches and offsets inherent in the sense amplifier, then the output may not produce the correct result during sensing. The incorrect results negatively impact yields at corners where bitline development is inadequate. The need exists for memory devices that consume less power and that can be implemented efficiently in integrated circuit designs.